View IRS2530D_8243544.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

july 09, 2008 IRS2530D(s) dim8 tm dimming ballast control ic ic features ? dimming ballast control plus half-bridge driver ? closed-loop lamp current dimming control ? internal non-zvs protection ? internal crest factor protection ? programmable preheat time ? fixed dead-time (2.0 s typ.) ? lamp insert auto-restart ? internal bootstrap mosfet ? internal 15.6v zener clamp diode on vcc ? micropower startup (250 a) ? latch immunity and esd protection ballast system features ? single chip dimming solution ? simple lamp current dimming control method ? single lamp current sensing resistor required ? no half-bridge current-sensing resistor required ? no external protection circuits required (fully internal) ? flash-free lamp start at all dimming levels ? large reduction in component count ? easy to use for fast design cycle time ? increased manufacturability and reliability typical connection diagram product summary topology half-bridge v offset 600 v v out v cc i o+ & i o- (typical) 180ma & 260ma deadtime (typical) 2.0 s package types pdip8 so8 typical applications ? linear dimming ballast (down to 10%) ? 3-way dimming ballast ? multi-level switch dimming ballast cres lres:a cdc rvcc1 lf cf br1 cbus l n f1 mls mhs dcp2 csnub dcp1 cvcc2 cbs rho rlo 1 2 3 4 8 7 6 5 IRS2530D vcc com dim vco lo vb vs ho rlmp2 rlmp1 cdim cvco cfb rdim2 spiral cfl lamp lres:b lres:c ch1 ch2 1-10v dim input rdim1 rcs rfb cph rvco (+) (-) ac line input rvcc2 cvcc1 rlim1 rlim2 www.irf.com ? 2008 international rectifier 1
IRS2530D(s) www.irf.com ? 2008 international rectifier 2 table of contents page description 3 qualification information 4 absolute maximum ratings 5 recommended operating conditions 6 electrical characteristics 7 input/output pin equivalent circuit diagram 9 lead definitions 10 lead assignments 10 state diagram 11 application information and additional details 12 package details 20 tape and reel details 21 part marking information 22 ordering information 23
IRS2530D(s) www.irf.com ? 2008 international rectifier 3 description this ic takes full advantage of ir?s patented ballast a nd high-voltage technologies to realize a simple, high- performance dimming ballast solution. a single high-v oltage pin senses the half-bridge current and voltage to perform necessary ballast protection functions. the dc dim input voltage reference and the ac lamp current feedback have been coupled together allowing a single pin to be used for dimming. combining these high-voltage control algorithms together with a simple dimming method in a single 8-pin ic results in a large reduction in component count, an increase in manufactu rability and reliability, a reduced design cycle time, while maintaining high dimming ballast system performance block diagram high-side half-bridge driver low-side half-bridge driver restart logic fault logic voltage controlled oscillator dimming control driver logic half-bridge voltage sensing non-zvs protection uvlo bootstrap mosfet 1 2 3 4 5 6 7 8vb ho vs lo vco dim com vcc 1ua crest factor protection
IRS2530D(s) www.irf.com ? 2008 international rectifier 4 qualification information ? industrial ?? qualification level comments: this family of ics has passed jedec?s industrial qualification. ir?s consumer q ualification level is granted by extension of the higher industrial level. soic8 msl2 ??? (per ipc/jedec j-std-020c) moisture sensitivity level pdip8 not applicable (non-surface mount package style) machine model class c (per jedec standard eia/jesd22-a115) esd human body model class 3a (per eia/jedec standard jesd22-a114) ic latch-up test class i, level a (per jesd78a) rohs compliant yes ? qualification standards can be found at international rectifier?s web site http://www.irf.com/ ?? higher qualification ratings may be available should the user have such require ments. please contact your international rectifier sales re presentative for further information. ??? higher msl ratings may be available for the specif ic package types listed here. please contact your international rectifier sales repres entative for further information.
IRS2530D(s) www.irf.com ? 2008 international rectifier 5 absolute maximum ratings absolute maximum ratings indicate sustained limit s beyond which damage to the device may occur. all voltage parameters are absolute voltages referenced to co m, all currents are defined positive into any lead. the thermal resistance and power dissipation rati ngs are measured under board mounted and still air conditions. symbol definition min. max. units v b high-side floating supply voltage -0.3 625 v s high-side floating supply offset voltage v b - 25 v b + 0.3 v ho high-side floating output voltage v s - 0.3 v b + 0.3 v lo low-side output voltage -0.3 v cc + 0.3 v vco vco input voltage ?? -0.3 6 v dim dim input voltage -0.3 v cc + 0.3 v i cc supply current ? --- 20 io max maximum allowable current at lo, ho and pfc due to external power transistor miller effect. -500 500 ma dv s /dt allowable vs pin voltage slew rate -50 50 v/ns p d maximum power dissipation @ t a +25oc, 8-pin dip --- 1.0 p d maximum power dissipation @ t a +25oc, 8-pin soic --- 0.625 w r ja thermal resistance, junction to ambient, 8-pin dip --- 85 r ja thermal resistance, junction to ambient, 8-pin soic --- 128 oc/w t j junction temperature -55 150 t s storage temperature -55 150 t l lead temperature (soldering, 10 seconds) --- 300 oc ? this ic contains a zener clamp structure bet ween the chip vcc and com which has a nominal breakdown voltage of 15.6v. this supply pin s hould not be driven by a dc, low impedance power source greater than the v clamp specified in the electrical characteristics section. ?? this ic contains a zener clamp structure bet ween the chip vco and com which has a nominal breakdown voltage of 7.25v. this pin should not be driven by a dc, low impedance power source greater than the v vcomax specified in the electrical characteristics section.
IRS2530D(s) www.irf.com ? 2008 international rectifier 6 recommended operating conditions for proper operation the device should be used within the recommended conditions. symbol definition min. max. units v bs high-side floating supply voltage v cc - 0.7 v clamp v v s steady state high-side floating supply offset voltage -3.0 ??? 600 v v cc supply voltage v ccuv+ + 0.1v v clamp v i cc supply current --- 5 ma v vco vco pin voltage 0 6 v t j junction temperature -40 125 oc ??? care should be taken to avoid output switching conditions where the v s node decreases below com by more than 5v.
IRS2530D(s) www.irf.com ? 2008 international rectifier 7 electrical characteristics vcc=vbs=14v, vs=0v, cvcc=cbs=0.1 f, cvco=cdim=10nf, clo=cho=1nf, and ta = 25c unless otherwise specified. the output voltage and current (v o and io) parameters are referenced to com and are applicable to the respective ho and lo output leads. symbol definition min typ max units test conditions low voltage supply characteristics v clamp v cc zener clamp voltage 14.6 15.6 16.6 i cc = 10ma v ccuv+ rising v cc uvlo+ threshold 11.5 12.5 13.5 v ccuv - falling v cc uvlo- threshold 9.5 10.5 11.5 v ccuvhy v cc undervoltage lockout hy steresis 1.5 2.0 3.0 v i qccuv micropower startup v cc supply current --- 250 --- a v cc = 8v i ccdim dim mode v cc supply current --- 4.5 --- ma mode = dim i qccflt fault mode v cc supply current --- 375 --- a mode = fault v vcomax vco pin zener clamp voltage --- 7.25 --- v mode = dim floating supply characteristics i bs v bs supply current --- 2 3 ma mode = dim i qbsuv uvlo mode vbs quiescent current --- --- 50 a vbs = 7v v bsuv+ rising v bs supply undervoltage threshold 8.0 9.0 10.0 v bsuv- falling v bs supply undervoltage threshold 7.0 8.0 9.0 v i lk offset supply leakage current --- --- 50 a v b = v s = 600v ballast control characteristics f min minimum output frequency 32.0 34.2 36.4 vco = 6v f max maximum output frequency --- 115 --- khz vco = 0v d duty cycle --- 50 --- % dt output deadtime (ho or lo ) --- 2.0 --- s mode = all i vco vco pin charging current --- 1 --- a mode = ph/ign v losd+ lo pin shutdown threshold --- 8.75 --- mode = fault v losd- lo pin re-start threshold --- 8.5 --- v mode = fault v zvsth vs non-zvs detection threshold --- 4.5 --- mode = dim, lo = high v vcoflt+ vco fault rising threshold --- 4.0 --- v mode = ph/ign cscf crest factor peak-to-average fault factor --- 5.5 --- n/a mode = dim vs offset = 0.5v
IRS2530D(s) www.irf.com ? 2008 international rectifier 8 electrical characteristics vcc=vbs=14v, vs=0v, cvcc=cbs=0.1 f, cvco=cdim=10nf, clo=ch o=1nf, and ta = 25c unless otherwise specified. the output voltage and current (v o and io) parameters are referenced to com and are applicable to the respective ho and lo output leads. symbol definition min typ max units test conditions dimming control characteristics v dimreg dim regulation threshold --- 0.0 --- v mode = dim gate driver output characteristics (ho and lo) v oh high-level output voltage --- vcc --- i o = 0a v ol low-level output voltage --- com --- i o = 0a v ol_uv uv-mode output voltage --- com --- i o = 0a, v cc v ccuv- t r output rise time --- 120 220 t f output fall time --- 50 80 t sd shutdown propagation delay --- 350 --- ns i o+ output source current --- 180 --- i o- output sink current --- 260 --- ma bootstrap fet characteristics vb_on vb when the bootstrap fet is on --- 13.3 --- v ib_cap vb source current when fet is on 30 55 --- cbs = 0.1f ib_10v vb source current when fet is on 8 12 --- ma vb = 10v
IRS2530D(s) www.irf.com ? 2008 international rectifier 9 i/o pin equivalent circuit diagrams
IRS2530D(s) www.irf.com ? 2008 international rectifier 10 lead definitions pin # symbol description 1 vcc logic and internal gate drive supply voltage 2 com ic power and signal ground 3 dim dimming dc reference and ac lamp current feedback input 4 vco voltage-controlled oscillator (vco) input 5 lo half-bridge low-side gate driver output 6 vs high voltage floating supply return and half-bridge sensing input 7 ho high-side gate driver output 8 vb high-side gate driver floating supply lead assignments com dim vco vcc 1 2 3 4 7 6 5 8 IRS2530D lo vs ho vb
IRS2530D(s) www.irf.com ? 2008 international rectifier 11 state diagram vcc < 10.5v (vccuv-) uvlo mode half -bridge off i qccuv ? 250 a vco = 0v ho off lo open circuit ph/ign mode half-bridge oscillating freq ramps from f max to f min vco charging (1 a) non-zvs disabled crest factor disabled vcc > 12.5v (vccuv+) and lo < 8.5v (vlosd-) (lamp inserted) power off fault mode fault latch set half-bridge off i qccuv ? 250 a ho off lo open circuit vcc < 10.5v (vccuv-) or lo > 8.75v (vlosd+) (lamp removed) lamp ignites cf > 5.5 (lamp removal) dim mode half-bridge oscillating @f dim dimming loop enabled non-zvs enabled crest factor enabled vcc > 0v zvs freq = freq + df non-zvs zvs ok vco > 4.0v (vvcoflt+) (lamp non-strike)
IRS2530D(s) www.irf.com ? 2008 international rectifier 12 application information and additional details information regarding the following topics is included as subsections within this section of the datasheet: ? uvlo mode and ic supply circuitry ? preheat/ignition (ph/ign) mode ? dim mode ? non zero-voltage switching (zvs) protection ? crest factor over-current protection ? fault mode and lamp reset ? component selection ? pcb layout guidelines uvlo mode and ic supply circuitry the under-voltage lock-out mode (uvlo) is defined as the state the ic is in when v cc is below the turn-on threshold of the ic, v ccuv+ (12.5 v, typical), and lo is above the shutdown threshold, v losd+ (8.75 v, typical). the uvlo circuit is designed to maintain an ultra-low supply current i qccuv (<250 a), and to guarantee that the ic is fully functional before the high- and low-side output gate drivers are activa ted. the vcc capacitor, cvcc, is charged up from the dc bus voltage throug h supply resistors rvcc1 and rvcc2 (figure 1). the values of these resistors are chosen such that vc c reaches the uvlo+ turn-on threshold voltage at the desired dc bus voltage level. once the capacitor voltage on vcc reaches the start-up threshold, v ccuv+ , the ic turns on and the ho and lo gat e drive outputs start oscillating. the capacitor cvcc should be large enough to hold the voltage at vcc above the v ccuv- threshold until the external aux iliary supply can take over and supply the required voltage and current to the ic. vcc com vco lo vs ho vb dim mhs cbs cvcc1 rvco rvcc2 dcp2 dcp1 csnub cvco mls dcbus(+) dcbus(-) 8 7 6 5 1 2 3 4 to load load return 15.6v clamp high- and low- side driver bootstrap fet driver uvlo vcc rho rlo cph cdim rvcc1 dim ref and fb cvcc2 rlim1 rlim2 figure 1, uvlo and supply circuitry. an external charge pump circuit consisting of ca pacitor csnub and diodes dcp1 and dcp2, comprises the auxiliary supply voltage for the low-side circuitry (figure 1). to limit high peak currents that can flow from the external charge pump to vcc, a zene r diode (18 v, typical) should be used for the lower charge pump diode, dcp1. also, two low-ohmic re sistors (rlim1 and rlim2, 10 ? each, typical) should be used together with cvcc1 and cvcc2 to further limit and filter fast current spikes to minimize resulting voltage spikes that can occur at vcc. an internal bootstrap mosfet between vcc and vb and external supply capacitor, cbs, determine the supply voltage for the high-side driver circui try (figure 1). the bootstrap mosfet is turned on when lo is ?high? and charges cbs from vcc each cycle to maintain the vb-to-vs voltage above the v bsuv- threshold (8 v, typical). the value of cbs should be chosen such that the vb-to-vs voltage and ripple stays above v bsuv- at all times. when vcc exceeds v ccuv+ for the first time, lo will firs t oscillate for several cycles
IRS2530D(s) www.irf.com ? 2008 international rectifier 13 until the vb-to-vs voltage exceeds the high-side uvlo rising threshold, v bsuv+ (9 v, typical), and the high- side driver is enabled. the capacitor cvcc should be large enough such that vcc does not reach uvlo- before ho is enabled and the charge pump supply takes over. external gate drive resistors, rho and rlo, are also recommended as standard design practice to limit high peak currents that can flow into or out of the ho and lo gate drive outputs. during uvlo mode, the high-side gate driver output, ho, is ?low? and the vco pin is pulled down internally to com. the low-side gate driver output, lo, is open circ uit and is used as a shutdown/reset input function for automatically restarting the ic when a lamp ha s been removed and re-inserted. the ic includes an internal shutdown threshold, v losd+ (8.75 v, typical), and re-start logic circuit at the lo pin that is only active during uvlo mode. if vcc is above v ccuv+ , but the lamp is removed, the external pull-up network (rlmp1 and rlmp2) will pull lo above v losd+ and the ic will remain in uvlo mode. when the lamp is re- inserted, the lower filament of the lamp will pull lo down below v losd- (8.5 v, typical) and the ic will exit uvlo mode and enter preheat/ignition mode. preheat/ignition (ph/ign) mode when vcc exceeds v ccuv+ and the lo pin is below v losd- , the ic enters preheat/ignition mode. an internal current source, i vco (1 a, typical), (figure 2) charges the external capacitor on pin vco causing the voltage on pin vco to start ramping up linearly. an additional quick-start current, i vcoqs (50 a, typical), is also connected to the vco pin and charges the vco pin initia lly to 0.85 v. the quick- start current charges the vco voltage up quickly to the internal 1 to 5 v range of the internal vco. when the vco voltage exceeds 0.85 v the quick-start current is t hen disconnected internally and the vco voltage continues to charge up with the normal frequency sweep current source, i vco (1 a, typical) (figure 3). vcc com vco lo vs ho vb dim mhs cbs cvcc2 rvco rvcc2 dcp2 dcp1 csnub cvco mls dcbus(+) dcbus(-) 8 7 6 5 1 2 3 4 to load load return 15.6v clamp high- and low- side driver bootstrap fet driver vco rho rlo cph cdim rvcc1 dim ref and fb 1ua fault logic + _ 4.6v cvcc1 rlim1 rlim2 figure 2, preheat/ignition mode circuitry. the frequency ramps down from the maximum frequency towards the resonance frequency of the high-q ballast output stage. the lamp filaments are preheat ed as the lamp voltage and load current increase. the voltage on pin vco continues to increase and the frequency keeps decreasing until the lamp ignites. if the lamp ignites successfully, the ic will then enter dim mode (figure 3).
IRS2530D(s) www.irf.com ? 2008 international rectifier 14 v vco 4.0v 0.85v freq fmax fmin preheat/ignition mode dim mode dc dim reference ac lamp current v dim v lamp lamp ignites v vcoflt+ figure 3, preheat/ignition/dim mode timing diagram. the resonant output stage transitions to a series-l, parallel-rc circuit with the q-value and operating point determined by the user dim level (figure 4). if the lamp does not ignite, the voltage on pin vco continues to increase and the frequency continues to decrease until the vco voltage exceeds v vcoflt+ (4.0v, typical) and the ic enters fault mode and shuts down. the mi nimum frequency should be set below the high-q resonance frequency of the ballast ou tput stage to ensure that the frequency ramps through resonance for lamp ignition (figure 4). the desired preheat time can be set by adjusting the slope of the vco ramp with the external capacitor, cph.
IRS2530D(s) www.irf.com ? 2008 international rectifier 15 high-q low-q start ignition vout vin frequency fmax f100% p r e h e a t f10% f50% 10% 50% 100% fmin figure 4, resonant tank bode plot with lamp dimming operating points. dim mode when the lamp ignites, the ballast output stage become s a series-l, parallel-rc circuit and the ac lamp current flows through the current sensing resistor, rcs. the resulting ac voltage across resistor rcs is coupled to the dim pin through feedback resistor, rfb (1 k ? , typical), and feedback capacitor, cfb (0.1 f, typical). the dim pin voltage is a combination of the dc offset voltage provided by the user dim setting and the ac voltage that is capacitively coupled through capa citor cfb from the lamp current sensing resistor to the dim pin. the ic enters dim mode when the lamp ignites and the dimming control loop becomes active. the dc+ac voltage at the dim pin is regulated by the co ntrol loop such that the valley of the ac voltage always stays at com. by offsetting the ac voltage with a dc reference and holding the valley of the ac voltage at com, the amplitude of the ac voltage, and therefore the ac lamp cu rrent, is accurately controlled. when the dc reference voltage at the dim pin is decre ased for dimming, the valleys of the ac voltage are pushed below com. the dimming control circuit increase s the frequency to decrease the ac lamp current until the ac valleys at the dim pin are at com again. when the dc reference is increased to increase the brightness level, the valleys of the ac voltage increa se above com. the dimming control circuit decreases the frequency to increase the ac lamp current until the ac valleys at the dim pin are at com again. in this way, the dimming control circuit keeps the ac lamp current peak-to-peak amplitude regulated to the desired value at all dc dim level settings. capacitor cvco pr ograms the speed of the dimming loop and is typically set to a low value (2.2 nf, typical) for cycle-by-cycle lamp current control. an additional compensation network is formed by rvco (1.5 k ? , typical) and cph to prevent the vco voltage from changing too much from one cycle to the next for maintaining smooth and st able dimming. a capacitor, cdim (10 nf, typical) is also necessary from the dim pin to com for filtering high-frequency switching noise. during dim mode, the vs-sensing circuit and non-zvs and crest factor protection circuits are also enabled (see state diagram, page 11). non zero-voltage switching (zvs) protection during dim mode, if the voltage at the vs pin has not slewed entirely to com during the dead-time such that there is voltage between the drain and source of the external low-side half-bridge mosfet when lo turns- on, then the system is operating too close to, or, on the ca pacitive side of resonance. the result is non-zvs capacitive-mode switching that causes high peak currents to flow in the half-bridge mosfets that can damage or destroy them (figure 5). this can typi cally occur during a decrease of the dc bus during an ac mains interrupt or brown-out condition, lamp variati ons over time, driving an incorrect lamp type, or component and temperature variations. to protect against this, an internal high-voltage mosfet is turned on at each turn-off of ho and the vs-sensing circuit m easures the vs voltage at each rising edge of lo. if the vs voltage is greater than v zvsth (4.5 v, typical), the non-zvs contro l circuit will increase the frequency until zvs is reached again. increasing the frequency due to non-zvs during a brown-out also ensures that
IRS2530D(s) www.irf.com ? 2008 international rectifier 16 that the ignition/preheat ramp will be reset to re-ignite the lamp reliably in case the dc bus decreases too far and the lamp extinguishes. lo ho i mls too close to resonance. hard-switching and high peak mosfet currents! ! i mhs vs i l frequency shifted higher to maintain zvs. ! ! figure 5, non-zvs protection timing diagram. crest factor over-current protection the IRS2530D uses the vs-sensing circuitry to also measure the low-side half-bridge mosfet current for detecting an over-current fault. by using the r dson of the external low-side mosfet for current sensing, the ic eliminates the need for an external current sensing resistor. to cancel changes in the r dson value due to temperature and mosfet variations, the ic performs a crest factor measurement that detects when the peak current exceeds the aver age current by a factor of 5.5 (cscf). measuring the crest factor is ideal for detecting when the inductor saturates due to excessive current that occurs in t he resonant tank when the frequency is too close to resonance. during dim mode, t he crest factor over-current protection is used to detect if the filaments fail, the lamp is removed, or the lamp becomes deact ivated. during each of these fault conditions, the output stage will transition to a series -lc configuration. the re sonant inductor, lres, and resonant capacitor, cres, remain connected together to form a complete circuit due to the voltage-mode heating configuration to the lamp (see typical app lication diagram, page 1). the frequency will move towards resonance until the inductor saturates. the crest factor protection circuit will then detect the saturation and the ic will enter fault mode and shut down. fault mode and lamp reset during fault mode the internal fault latch is set, ho is off, lo is open circuit, and the ic consumes an ultra- low micro-power current (see state diagram, page 11) . the ic can be reset with a lamp exchange (as detected by the lo pin) or a recycling of vcc bel ow and back above the uvlo thresholds. during fault mode, the lo pin is open circuit and is used as an input pin for resetting the ic. if the lamp is removed, the external pull-up network at the lower lamp filamen t, rlmp1 and rlmp2 (see typi cal application diagram, page 1), will pull lo above v losd+ (8.75v, typical) and the ic will exit fault mode and enter uvlo mode. when the lamp is re-inserted, the lower f ilament of the lamp will pull lo down below v losd- (8.5v, typical) and the ic will exit uvlo mode and enter preheat/ignition mode and restart the lamp.
IRS2530D(s) www.irf.com ? 2008 international rectifier 17 component selection proper design of the circuit schematic (see typical application diagram, page 1) and component selection is important for achieving proper ballast functionality and preventing problems. the following design procedure should be followed for determining the various programming and filtering component values: 1) capacitor cph programs the desired preheat/igni tion time. cph is charged up by an internal 1 a current source at the vco pin. the value of cph is determined by: v ta v ti c ignph vcoflt ignphvco ph 4 1 / / ? = ? = 2) capacitor cvco programs the speed of the dimming feedback loop. to ensure smooth and stable dimming, cvco should be small enough such that the dimming loop reacts to lamp current changes each switching cycle. the value of cvco is typica lly fixed for most lamp types and is given as: nf c vco 2.2 = 3) resistor rvco and capacitor cp h provide additional compensation of the dimming loop to prevent the vco voltage from changing too much over a gi ven switching cycle. the value of rvco is typically fixed for most lamp types and is given as: = kr vco 5.1 4) resistor rcs measures the lamp current for di mming. rcs should be kept small to minimize power losses but the peak voltage across rcs at the lo west lamp current dimming level should be above a minimum level to avoid noise problems. using t he minimum rms lamp current during dimming, a minimum allowable peak voltage level across rcs of 100 mv, and an additional factor of 5 (signal attenuation due to rfb and cdim), the value of rcs is determined by: 5 2 100 __ ? = minrms lamp cs i mv r using the maximum rms lamp current, the po wer loss in resistor rcs is then determined by: cs maxrms lamp rcs loss r i p = 2 __ _ ) ( 5) the additional feedback components include rfb for current limiting and noise filtering, cfb for dc blocking, and cdim for noise filtering. the value of these components are ty pically fixed for most lamp types and are given as: = kr fb 1 f c fb 1.0 = nf c dim 10 = 6) capacitors cvcc2 and cbs are the low-side and hi gh-side supply capacitors for maintaining their respective supply voltages and providing high-fr equency noise filtering. these capacitors are typically fixed and are given as: f cc bs vcc 1.0 2 = =
IRS2530D(s) www.irf.com ? 2008 international rectifier 18 component selection (continued) 7) resistors rvcc1 and rvcc2 pr ovide the micro-power supply current to vcc and therefore determine the ac line input voltage where the ballast first turns on. the value of these resistors is determined by: ua vccuv vac rr on vcc vcc 250 2 2 1 + ?? =+ 8) the additional supply components include capa citor cvcc1 for holding up vcc until the charge pump takes over, charge pump capacitor csnub fo r providing vcc supply current, charge pump diodes dcp1 and dcp2, and limiting re sistors rlim1 and rlim2 for preventing high currents from flowing into vcc. these components are typica lly fixed for most design and are given as: fc vcc 1 1 = kvnfc snub 1/1 = mwvd cp 500/18 1 = 41481 2 nd cp = = = 10 2 1 lim lim rr 9) resistors rlmp1 and rlmp2 prov ide the necessary pull-up signal to the lo pin for detecting the removal and insertion of the lower lamp filament. both of these resistor should be high-ohmic to minimize current flow from vcc and to minimize cu rrent flow from the low-side filament to the lo pin. these resistor values are typically fixed and are given as: = k r lmp 470 1 = mr lmp 1 2
IRS2530D(s) www.irf.com ? 2008 international rectifier 19 pcb layout guidelines proper care should be taken when laying out a pcb board to minimize noise effects due to high-frequency switching and to ensure proper functionality of the IRS2530D. rcs rfb cfb cvcc2 cvco rvco cdim cph cbs rlo rho rlim2 rlim1 cvcc1 rvcc1 rlmp2 rlmp1 csnub dcp2 dcp1 rvcc2 (+) dc bus (-) dc bus half-bridge output (vs) power ground lamp return filament sensing (+) (-) mls mhs dim input ic com connects to power gnd at single point 1 vcc charge pump circuitry high-voltage, high-current and high-frequency half-bridge output ic and programming components lamp current sensing and feedback high-side gnd (vs) connects to half-bridge mid-point at single point adjacent com trace for additional noise filtering of feedback signal. figure 9, typical through-hole and smd single-laye r pcb layout for application diagram, page 1 (bottom copper layer shown from top view). the programming components for the ic should be connected to the ic com pin and then connected to power ground at a single point (figure 9). the la mp current sensing feedback components (rfb, cfb) should be kept as far away as possible from t he high-voltage/high-frequency half-bridge components to prevent switching noise from distorting the lamp curre nt feedback signal. adjacent ground traces to the feedback signals can also help reduce switching noi se. in general, the following guidelines should be followed during pcb board layout: 1) place all ic supply capacitors (cvcc2, cbs) and as close as possible to their respective supply and return pins (cvcc, cbs). 2) place all ic programming and filter components as close as possible between their respective pins and com (cvco, rvco, cph, cdim, cfb, rfb). 3) connect ic com to power gnd at one connection only. do not route power gnd through the programming components or ic com! 4) connect high-side gate-drive ground (vs) to hal f-bridge mid-point at one connection only. do not route high-side power ground through the vs components or vs pin. 5) connect the anode of charge pump diode dcp1 to power ground. do not connect to ic com. 6) use gate resistors (rlo, rho) between all gate driver output s and the gate of their respective power mosfets. 7) use zener diode (18 v, typical) for lower charge pump diode (dcp1) and limiting resistors and capacitors (rlim1, cvcc1, rlim2, cvcc2) to filter high current spikes that can cause large voltage spikes to occur on vcc.
IRS2530D(s) www.irf.com ? 2008 international rectifier 20 package details
IRS2530D(s) www.irf.com ? 2008 international rectifier 21 tape and reel details: soic8n e f a c d g a b h n ote : controlling dimension in mm loaded tape feed direction a h f e g d b c carrier tape dimension for 8soicn code min max min max a 7.90 8.10 0.311 0.318 b 3.90 4.10 0.153 0.161 c 11.70 12.30 0.46 0.484 d 5.45 5.55 0.214 0.218 e 6.30 6.50 0.248 0.255 f 5.10 5.30 0.200 0.208 g 1.50 n/a 0.059 n/a h 1.50 1.60 0.059 0.062 metric imperial reel dimensions for 8soicn code min max min max a 329.60 330.25 12.976 13.001 b 20.95 21.45 0.824 0.844 c 12.80 13.20 0.503 0.519 d 1.95 2.45 0.767 0.096 e 98.00 102.00 3.858 4.015 f n/a 18.40 n/a 0.724 g 14.50 17.10 0.570 0.673 h 12.40 14.40 0.488 0.566 metric imperial
IRS2530D(s) www.irf.com ? 2008 international rectifier 22 part marking information irsxxxxx ir logo yww ? part number date code pin 1 identifier lot code (prod mode ? 4 digit spn code) assembly site code per scop 200-002 ? xxxx marking code lead free released non-lead free released ? p
IRS2530D(s) www.irf.com ? 2008 international rectifier 23 ordering information standard pack base part number package type form quantity complete part number pdip8 tube/bulk 50 IRS2530Dpbf tube/bulk 95 IRS2530Dspbf IRS2530D soic8n tape and reel 2500 IRS2530Dstrpbf the information provided in this document is believed to be accu rate and reliable. however, international rectifier assumes no responsibility for the consequences of the use of this information. international rectifier assumes no responsibility for any infringement of patents or of other rights of third parties which may result from the use of this information. no license is g ranted by implication or otherwise under any patent or patent rights of inte rnational rectifier. the spec ifications mentioned in this do cument are subject to change without notice. th is document supersedes and replaces all informati on previously supplied. for technical support, please contact ir?s technical assistance center http://www.irf.com/technical-info/ world headquarters: 233 kansas st., el segundo, california 90245 tel: (310) 252-7105

▲Up To Search▲

Price & Availability of IRS2530D

	To Download IRS2530D Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .